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general description the max1270/max1271 are multirange, 12-bit data- acquisition systems (das) that require only a single +5v supply for operation, yet accept signals at their analog inputs that may span above the power-supply rail and below ground. these systems provide eight analog input channels that are independently software pro- grammable for a variety of ranges: ?0v, ?v, 0 to +10v, 0 to +5v for the max1270; ? ref , ? ref /2, 0 to v ref , 0 to v ref /2 for the max1271. this range switch- ing increases the effective dynamic range to 14 bits and provides the flexibility to interface 4?0ma, ?2v, and ?5v powered sensors directly to a single +5v system. in addition, these converters are fault protected to ?6.5v; a fault condition on any channel will not affect the conversion result of the selected channel. other fea- tures include a 5mhz bandwidth track/hold, software- selectable internal/external clock, 110ksps throughput rate, and internal 4.096v or external reference opera- tion. the max1270/max1271 serial interface directly con- nects to spi/qspi and microwire devices with- out external logic. a hardware shutdown input ( shdn ) and two software- programmable power-down modes, standby (stbypd) or full power-down (fullpd), are provided for low-cur- rent shutdown between conversions. in standby mode, the reference buffer remains active, eliminating start-up delays. the max1270/max1271 are available in 24-pin narrow dip or space-saving 28-pin ssop packages. applications industrial control systems data-acquisition systems robotics automatic testing battery-powered instruments medical instruments features 12-bit resolution, 1/2lsb linearity +5v single-supply operation spi/qspi and microwire-compatible 3-wire interface four software-selectable input ranges max1270: 0 to +10v, 0 to +5v, 10v, 5v max1271: 0 to v ref , 0 to v ref /2, v ref , ? ref /2 eight analog input channels 110ksps sampling rate 16.5v overvoltage-tolerant input multiplexer internal 4.096v or external reference two power-down modes internal or external clock 24-pin narrow dip or 28-pin ssop packages max1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ____________________________________________________________ maxim integrated products 7-169 typical operating circuit 19-4782; rev 1; 3/99 part max1270 acng max1270bcng max1270acai 0? to +70? 0? to +70? 0? to +70? temp. range pin-package 24 narrow plastic dip 24 narrow plastic dip 28 ssop evaluation kit manual follows data sheet ordering information continued at end of data sheet. ordering information pin configurations appear at end of data sheet. inl (lsb) ?/2 ? ?/2 max1270bcai 0? to +70? 28 ssop ? v dd ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 dgnd 0.01 f 4.7 f 0.1 f shdn max1270 max1271 +5v analog inputs cs sclk din dout sstrb i/o sck mosi miso ref refadj agnd mc68hcxx spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769.
db max1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 7-170 ___________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +5.0v ?%; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7? at ref; external clock, f clk = 2.0mhz (50% duty cycle), 18 clock/conversion cycle, 110ksps; t a = t min to t max ; unless otherwise noted. typical values are t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd............................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v ch0?h7 to agnd ......................................................... ?6.5v ref, refadj to agnd ..............................-0.3v to (v dd + 0.3v) sstrb, dout to dgnd.............................-0.3v to (v dd + 0.3v) shdn , cs , din, sclk to dgnd..............................-0.3v to +6v max current into any pin ....................................................50ma continuous power dissipation (t a = +70?) 24-pin narrow dip (derate 13.33mw/? above +70?) ..1067mw 28-pin ssop (derate 9.52mw/? above +70?) ..........762mw operating temperature ranges max127_c_ _ ......................................................0? to +70? max127_e_ _....................................................-40? to +85? storage temperature range ............................-65? to +150? lead temperature (soldering, 10sec) ............................+300? max127_b lsb ?.1 max127_a channel-to-channel offset error matching up to the 5th harmonic db -87 -78 thd total harmonic distortion unipolar max127_a bipolar max127_b no missing codes over temperature unipolar conditions bipolar unipolar, external reference bipolar, external reference ?0 lsb ? ?.3 gain error (note 2) db 70 sinad signal-to-noise + distortion ratio dynamic specifications ? ?0 ppm/? ? gain error temperature coefficient (note 2) ? dc, v in = ?6.5v 50khz (note 3) lsb ?.5 inl integral nonlinearity bits 12 accuracy (note 1) resolution external clock mode external clock mode ?0 ? ?.0 lsb ? dnl differential nonlinearity lsb ? offset error ? units min typ max symbol parameters internal clock mode -96 db -86 db 80 sfdr spurious-free dynamic range channel-to-channel crosstalk ns 15 aperture delay ps <50 aperture jitter ns 10 max127_a max127_b max127_a max127_b unipolar bipolar max127_a max127_b accuracy (note 1) dynamic specifications (10khz sine-wave input, ?0vp-p (max1270), or ?.096vp-p (max1271), f sample = 110ksps)
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-171 electrical characteristics (continued) (v dd = +5.0v ?%; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7? at ref; external clock, f clk = 2.0mhz (50% duty cycle), 18 clock/conversion cycle, 110ksps; t a = t min to t max ; unless otherwise noted. typical values are t a = +25?.) fullpd normal or stbypd ? ref /2 range max1271 ? ref range ?v range max1270 ?0v range max1271 0 to 5v range max1270 0 to 10v range max1271 rng = 1 max1270 rng = 1 max1271 rng = 1 ?0v or ? ref range ?v or ? ref / 2 range 0 to 10v or 0 to v ref range rng = 1 max1270 0 to 5v or 0 to v ref / 2 range 1 internal reference input capacitance 40 pf 16 dynamic resistance ? v in / ? i in 21 k ? ref output voltage v ref 4.076 4.096 4.116 v ref output tempco tc v ref ?5 ppm/? -600 360 -1200 10 -600 10 buffer voltage gain 1.638 v/v refadj adjustment range ?.5 % refadj output voltage 2.465 2.500 2.535 v capacitive bypass at refadj 0.01 ? reference input (reference input voltage range 2.40 4.18 v load regulation (note 5) output short circuit current 30 ma 10 mv capacitive bypass at ref 4.7 ? figure 1 (note 4) bipolar unipolar t a = +25? max1270_c/max1271_c 0 to 0.5ma output current input current 400 ? v ref = 4.18v ?0 max1270_e/max1271_e analog input track/hold acquisition time t acq 3 ? small-signal bandwidth 5 mhz input current i in -10 720 ? -v ref v ref -10 10 0v ref -10 360 -10 0.1 10 2.5 1.25 input voltage range v in 010 v unipolar bipolar (bip = 1), table 3 parameters symbol min typ max units f clk = 2.0mhz -3db rolloff unipolar (bip = 0), table 3 -1200 720 bipolar 2.5 conditions analog input internal reference reference input (reference buffer disabled, reference input applied to ref) rng = 0 05 0v ref /2 rng = 0 rng = 0 rng = 0 -5 5 -v ref /2 v ref /2
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs 7-172 ___________________________________________________________________________________ electrical characteristics (continued) (v dd = +5.0v ?%; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7? at ref; external clock, f clk = 2.0mhz (50% duty cycle), 18 clock/conversion cycle, 110ksps; t a = t min to t max ; unless otherwise noted. typical values are t a = +25?.) c ref = 33? c ref = 4.7? fullpd normal or stbypd reference buffer settling time 8 ms bandgap reference start-up time (note 9) 200 ? 60 digital inputs: din, sclk, 0.4 output voltage low v ol 0.4 v digital outputs: dout, input capacitance c in 15 pf output voltage high v oh v dd - 0.5 v three-state leakage current i l -10 10 ? input hysteresis input low threshold voltage v il 0.8 v v hys 0.2 v input leakage current i in -10 10 ? i sink = 16ma i sink = 5ma (note 4) i source = 0.5ma cs = v dd power-up three-state output capacitance c out v in = 0 to v dd 15 pf cs = v dd (note 4) input high threshold voltage v ih 2.4 v supply current i dd 18 supply voltage v dd 4.75 5.25 v power requirement refadj threshold for buffer disable v dd - 0.5 v 610 input resistance 10 k ? 4.18 m ? conversion time t conv 6 ? 35 acquisition phase 3 ? external clock frequency range f clk 0.1 2.0 mhz 6 7.7 11 throughput rate 110 ksps power-supply rejection ratio (note 7) psrr ?.1 ?.5 ?.5 timing external clock mode (note 8) internal clock mode, figure 9 external clock mode (note 8) internal clock mode, figure 9 normal external clock mode stbypd power down mode (note 6) external reference = 4.096v internal reference 43 internal clock mode v ref = 4.18v 120 220 fullpd power down mode symbol min typ max units conditions to 0.1mv, ref bypass capacitor fully discharged unipolar range bipolar range power requirement digital inputs: din, sclk, cs , shdn digital outputs: dout, sstrb ma parameters lsb 700 850 ? timing
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-173 timing characteristics (v dd = +4.75v to +5.25; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7? at ref; external clock, f clk = 2mhz; t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) (figures 2, 5, 7, 10) din to sclk setup t ds 100 din to sclk hold t dh 0 sclk fall to output data valid t do c load = 100pf 20 170 cs fall to output enable t dv c load = 100pf 120 cs rise to output disable t tr c load = 100pf 100 cs to sclk rise setup t css 100 cs to sclk rise hold t csh 0 sclk pulse width high t ch 200 sclk pulse width low t cl 200 sclk fall to sstrb t sstrb c load = 100pf 200 cs to sstrb output enable t sdv c load = 100pf external clock mode only 200 cs to sstrb output disable t str c load = 100pf external clock mode only 200 ns ns ns ns ns ns ns ns ns ns ns ns sstrb rise to sclk rise (note 4) t sck internal clock mode only 0 ns parameters symbol conditions min typ max units note 1: accuracy specifications tested at v dd = +5.0v. performance at power-supply tolerance limit is guaranteed by power-supply rejection test. note 2: external reference: v ref = 4.096v, offset error nulled. ideal last-code transition = fs - 3/2lsb. note 3 : ground ?n?channel; sine wave applied to all ?ff?channels. v in = ?v (max1270), v in = ?v (max1271). note 4: guaranteed by design, not production tested. note 5: use static external loads during conversion for specified accuracy. note 6: tested using internal reference. note 7: psrr measured at full scale. tested for the ?0v (max1270) and ?.096v (max1271) input ranges. note 8: acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (figure 6). note 9: not production tested. provided for design guidance only.
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs 7-174 ___________________________________________________________________________________ typical operating characteristics (typical operating circuit, v dd = +5v; external reference mode, v ref = +4.096v; 4.7? at ref; external clock, f clk = 2mhz; 110ksps; t a = +25?; unless otherwise noted.) 0 5 15 10 20 25 02 1 34567 supply current vs. supply voltage max1270/1 toc01 supply voltage (v) supply current (ma) 5.5 5.7 6.1 5.9 6.3 6.5 -40 10 -15 35 60 85 supply current vs. temperature max1270/1 toc02 temperature (?) supply current (ma) 50 150 450 350 250 650 550 750 -40 10 -15 35 60 85 standby supply current vs. temperature max1270/1 toc03 temperature ( c) standby supply current ( a) internal reference external reference 50 70 110 90 130 150 -40 10 -15 35 60 85 full power-down supply current vs. temperature max1270/1 toc04 temperature ( c) full power-down supply current ( a) internal reference external reference 0.1 0.2 0.6 0.5 0.4 0.3 0.7 0.8 -40 10 -15 35 60 85 channel-to-channel gain-error matching vs. temperature max1270/1 toc07 temperature ( c) channel-to-channel gain-error matching (lsb) bipolar mode unipolar mode 0.996 0.997 0.999 0.998 1.000 1.001 -40 10 -15 35 60 85 normalized reference voltage vs. temperature max1270/1 toc05 temperature ( c) normalized reference voltage 0 0.05 0.25 0.20 0.15 0.10 0.30 0.35 -40 10 -15 35 60 85 channel-to-channel offset-error matching vs. temperature max1270/1 toc06 temperature ( c) channel-to-channel offset-error matching (lsb) bipolar mode unipolar mode -0.15 -0.10 0.05 0 -0.05 0.10 0.15 0 1638 819 2457 3276 4095 integral nonlinearity vs. digital code max1270/1 toc08 digital code integral nonlinearity (lsb) -120 -100 -40 -60 -80 -20 0 0 20k 10k 30k 40k 50k ftt plot max1270/1 toc09 frequency (hz) amplitude (db) f in = 10khz f sample = 110ksps
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-175 0 1 2 3 4 5 6 7 8 0.1 1 10 100 1000 average supply current vs. conversion rate (using standby) max1270-toc10 conversion rate (ksps) average supply current (ma) v dd = 5v, internal reference, f clk = 2mhz external clock mode. low-range unipolar mode. v ch_ = 0 typical operating characteristics (continued) (typical operating circuit, v dd = +5v; external reference mode, v ref = +4.096v; 4.7? at ref; external clock, f clk = 2mhz; 110ksps; t a = +25?; unless otherwise noted.) 0 1 2 3 4 5 6 7 8 0.1 1 10 100 1000 average supply current vs. conversion rate (using fullpd) max1270-toc11 conversion rate (ksps) average supply current (ma) v dd = 5v, internal reference, f clk = 2mhz external clock mode. low-range unipolar mode. v ch_ = 0 pin description ssop dip pin function 14 15?1, 23 26 27 9 10 12 13 6 5 1 4, 7, 8, 11, 22, 24, 25, 28 2, 3 analog ground agnd 12 analog input channels ch0 ch7 13?0 bandgap voltage-reference output/external adjust pin. bypass with a 0.01? capacitor to agnd. connect to v dd when using an external reference at ref. refadj 21 reference-buffer output/adc reference input. in internal reference mode, the reference buffer pro- vides a 4.096v nominal output, externally adjustable at refadj. in external reference mode, disable the internal reference by pulling refadj to v dd and applying the external reference to ref. ref 23 serial data input. data is clocked in on the rising edge of sclk. din 7 serial strobe output. in internal clock mode, sstrb goes low after the falling edge of the eighth sclk and returns high when conversion is done. in external clock mode, sstrb pulses high for one clock period before the msb decision. high impedance when cs is high in external clock mode. sstrb 8 serial data output. data is clocked out on the falling edge of sclk. high impedance when cs is high. dout 10 shutdown input. when low, device is in fullpd mode. connect high for normal operation. shdn 11 active-low chip-select input. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. cs 6 serial clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. sclk 5 1 no connect. no internal connection. n.c. 3, 9, 22, 24 digital ground dgnd 2, 4 +5v supply. bypass with a 0.1? capacitor to agnd. v dd name
max1270/max1271 detailed description converter operation the max1270/max1271 multirange, fault-tolerant adcs use successive approximation and internal track/hold (t/h) circuitry to convert an analog signal to a 12-bit digital output. figure 3 shows the block diagram of the max1270/max1271. analog-input track/hold the t/h enters tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word, and enters hold/conversion mode when the timed acquisition interval (six clock cycles, 3s minimum) ends. in internal clock mode, the acquisition is timed by two external clock cycles and four internal clock cycles. when operating in bipolar (max1270 and max1271) or unipolar mode (max1270) the signal applied at the input channel is rescaled through the resistor-divider network formed by r1, r2, and r3 (figure 4); a low- impedance (<4 ? ) input source is recommended to minimize gain error. when the max1271 is configured for unipolar mode, the channel input resistance (r in ) becomes a fixed 5.12k ? (typ). source impedances below 15k ? (0 to v ref ) and 5k ? (0 to v ref /2) do not significantly affect the ac performance of the adc. the acquisition time (t acq ) is a function of the source output resistance, the channel input resistance, and the t/h capacitance. higher source impedances can be used if an input capacitor is connected between the analog inputs and agnd. note that the input capacitor forms an rc filter with the input source impedance, lim- iting the adc? signal bandwidth. multirange, +5v, 8-channel, serial 12-bit adcs 7-176 ___________________________________________________________________________________ 100k 510k 24k refadj +5v 0.01 f max1270 max1271 0.5ma dout or sstrb +5v a) high-z to v oh , v ol to v oh , and v oh to high-z b) high-z to v oh , v ol to v oh , and v oh to high-z c load c load 5ma dout or sstrb figure 1. reference-adjust circuit figure 2. output load circuit for timing characteristics ch2 ch1 ch0 shdn ch3 ch4 ch5 ch6 ch7 refadj ref v dd agnd dgnd max1270 max1271 12-bit sar adc in ref clock out t/h 2.5v reference analog input mux and signal conditioning av = 1.638 int clock din sstrb dout cs sclk serial interface logic 10k +4.096v figure 3. block diagram
input bandwidth the adc? input small-signal bandwidth depends on the selected input range and varies from 1.5mhz to 5mhz (see electrical characteristics ). the max1270/ max1271 maximum sampling rate is 110ksps. by using undersampling techniques, it is possible to digitize high-speed transient events and measure periodic sig- nals with bandwidths exceeding the adc? sampling rate. to avoid high-frequency signals being aliased into the frequency band of interest, anti-aliasing filtering is rec- ommended. input range and protection the max1270/max1271 have software-selectable input ranges. each analog input channel can be indepen- dently programmed to one of four ranges by setting the appropriate control bits (rng, bip) in the control byte (table 1). the max1270 has selectable input ranges extending to ?0v (? ref 2.441), while the max1271 has selectable input ranges extending to ? ref . figure 4 shows the equivalent input circuit. a resistor network on each analog input provides ?6.5v fault protection for all channels. whether or not the channel is on, this circuit limits the current going into or out of the pin to less than 2ma. this provides an added layer of protection when momentary overvolt- ages occur at the selected input channel, when a neg- ative signal is applied to the input, and when the device is configured for unipolar mode. the overvoltage pro- tection is active even if the device is in power-down mode or if v dd = 0. digital interface the max1270/max1271 feature a serial interface that is fully compatible with spi/qspi and microwire devices. for spi/qspi, set cpol = 0, cpha = 0 in the spi control registers of the microcontroller. figure 5 shows detailed serial interface timing information. refer to table 1 for programming the input control byte. max1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-177 figure 4. equivalent input circuit r3 5.12k r2 r1 ch_ s1 s2 s3 s4 bipolar unipolar voltage reference t/h out hold track track hold off on c hold s1 = bipolar/unipolar switch s2 = input mux switch s3, s4 = t/h switch 12.5k ? (max1270) or 5.12k ? (max1271) 8.67k ? (max1270) or (max1271) r1 = r2 = ? ? ? ? ? ? ? ? ? ? ? ? cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh figure 5. detailed serial-interface timing
v ref 2.4414 range and polarity max1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 7-178 ___________________________________________________________________________________ table 1. control-byte format table 2. channel selection table 3. range and polarity selection for max1270/max1271 range and polarity input range rng bip negative full scale zero scale (v) full scale 0 to 5v 0 0 0 v ref 1.2207 0 to 10v 1 0 0 ?v 0 1 -v ref 1.2207 0 v ref 1.2207 ?0v 1 1 -v ref 2.4414 0 v ref 2.4414 input range rng bip negative full scale zero scale (v) full scale 0 to v ref /2 0 0 0 v ref /2 0 to v ref 1 0 0 v ref ? ref /2 0 1 -v ref /2 0 v ref /2 ? ref 1 1 -v ref 0 v ref table 4. power down and clock selection range and polarity selection for max1270 range and polarity selection for max1271 start 3 select clock and power-down modes (table 4). pd1, pd0 1, 0 (lsb) selects unipolar or bipolar conversion mode (table 3). bip 2 selects the full-scale input voltage range (table 3). rng these three bits select the desired ?n?channel (table 2). sel2, sel1, sel0 6, 5, 4 first logic ??after cs goes low defines the beginning of the control byte. start 7 (msb) description name bit pd0 pd1 bip rng sel0 sel1 sel2 bit 0 (lsb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 (msb) ch7 1 1 1 ch6 0 1 1 ch5 1 0 1 ch4 0 0 1 ch3 1 1 0 ch2 0 1 0 ch1 1 0 0 ch0 0 0 0 channel sel0 sel1 sel2 full power-down mode (fullpd), clock mode unaffected 1 1 standby power-down mode (stbypd), clock mode unaffected 0 1 normal operation (always on), external clock mode 1 0 normal operation (always on), internal clock mode 0 0 mode pd0 pd1
input data format input data (control byte) is clocked in at din at the ris - ing edge of sclk. c s enables communication with the max1270/max1271. after cs falls, the first arriving logic ??bit represents the start bit (msb) of the input control byte. the start bit is defined as: the first high bit clocked into din with cs low anytime the converter is idle; e.g., after v dd is applied. or the first high bit clocked into din after bit 6 (d6) of a conversion in progress is clocked onto dout. output data format output data is clocked out on the falling edge of sclk at dout, msb first (d11). in unipolar mode, the output is straight binary. for bipolar mode, the output is two?- complement binary. for output binary codes, refer to the transfer function section. how to start a conversion the max1270/max1271 use either an external serial clock or the internal clock to complete an acquisition and perform a conversion. in both clock modes, the external clock shifts data in and out. refer to table 4 for programming clock modes. the falling edge of cs does not start a conversion on the max1270/max1271; a control byte is required for each conversion. acquisition starts after the sixth bit is programmed in the input control byte. conversion starts when the acquisition time, six clock cycles, expires. keep cs low during successive conversions. if a start- bit is received after cs transitions from high to low, but before the output bit 6 (d6) becomes available, the cur- rent conversion will terminate and a new conversion will begin. external clock mode (pd1 = 0, pd0 = 1) in external clock mode, the clock shifts data in and out of the max1270/max1271 and controls the acquisition and conversion timings. when acquisition is done, sstrb pulses high for one clock cycle and conversion begins. successive-approximation bit decisions appear at dout on each of the next 12 sclk falling edges (figure 6). additional sclk falling edges will result in zeros appearing at dout. figure 7 shows the sstrb timing in external clock mode. sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb and dout will output a logic low. the conversion must be completed in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. use internal clock mode if the clock period exceeds 10?, or if serial-clock inter- ruptions could cause the conversion interval to exceed 120?. the fastest the max1270/max1271 can run is 18 clocks per conversion in external clock mode, and with a clock rate of 2mhz, the maximum sampling rate is 111 ksps (figure 8). in order to achieve maximum throughput, keep cs low, use external clock mode with a continuous sclk, and start the following control byte after bit 6 (d6) of the conversion in progress is clocked onto dout. if cs is low and sclk is continuous, guarantee a start bit by first clocking in 18 zeros. max1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-179 sstrb cs sclk din dout 1 8 12 13 14 24 25 start sel2 sel1 sel0 bip rng pd1 pd0 lsb d11 msb msb d10 d9 d1 d0 lsb acquisition 6 sclk filled with zeros conversion 12 sclk a/d state high-z high-z high-z high-z figure 6. external clock mode, 25 clocks/conversion timing
max1270/max1271 internal clock mode (pd1 = 0, pd0 = 0) in internal clock mode, the max1270/max1271 gener - ate their conversion clock internally. this frees the microprocessor from the burden of running the acquisi- tion and the sar conversion clock, and allows the con- version results to be read back at the processor? convenience, at any clock rate from 0 to typically 10mhz. sstrb goes low after the falling edge of the last bit (pd0) of the control byte has been shifted in, and returns high when the conversion is complete. acquisition is completed and conversion begins on the falling edge of the 4th internal clock pulse after the con- trol byte; conversion ends on the falling edge of the 16th internal clock pulse (12 internal clock cycle pulses are used for conversion). sstrb will remain low for a maximum of 15?, during which time sclk should remain low for best noise performance. an internal reg- ister stores data while the conversion is in progress. the msb of the result byte (d11) is present at dout starting at the falling edge of the last internal clock of conversion. successive falling edges of sclk will shift the remaining data out of this register (figure 9). additional sclk edges will result in zeros on dout. when internal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. pulling cs high prevents data from being clocked in and three-states dout, but does not adversely affect a multirange, +5v, 8-channel, serial 12-bit adcs 7-180 ___________________________________________________________________________________ ? ? ? ? ? ? ? ? ? ? ? ? t sdv t sstrb sclk 12 t str sstrb sclk cs t sstrb ? ? ? ? ? ? ? ? high-z high-z figure 7. external clock mode sstrb detailed timing cs sclk din dout a/d state ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1813 19 24 26 31 32 14 16 37 start sel2 sel1 sel0 bip rng pd1 pd0 d11 d10 d9 d7 d8 d6 d5 d4 d2 d3 d1 d0 lsb msb lsb msb start sel2 sel1 sel0 bip rng pd1 pd0 start sel2 control byte result control byte 1 control byte 2 18 sclk 18 sclk sstrb d10 d11 d9 d8 d6 d7 d5 result 1 acquisition 6 sclk conversion 12 sclk acquisition 6 sclk conversion 12 sclk high-z high-z figure 8. external clock mode, 18 clocks/conversion timing
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-181 sstrb cs sclk din dout 18 20 start sel2 sel1 sel0 rng bip pd1 pd0 d11 d10 d1 d0 acquisition filled with zeros conversion a/d state 910 19 16 int clk 12 int clk msb lsb msb lsb 2 ext sclk +4 int clk high-z high-z high-z figure 9. internal clock mode, 20 sclk/conversion timing sclk #8 t sstrb t csh t sck ? ? ? ? ? ? t css note: for best noise performance, keep sclk low during conversion. ? ? ? sstrb sclk cs figure 10. internal clock mode sstrb detailed timing conversion in progress. figure 10 shows the sstrb timing in internal clock mode. internal clock mode conversions can be completed with 13 external clocks per conversion but require a waiting period of 15? for the conversion to be com- pleted (figure 11). most microcontrollers require that conversions occur in multiples of 8 sclk clock cycles; 16 clock cycles per conversion, as shown in figure 12, will typically be the most convenient way for a microcontroller to drive the max1270/max1271. applications information power-on reset the max1270/max1271 power up in normal operation (all internal circuitry active) and internal clock mode, waiting for a start bit. the contents of the output data register are cleared at power-up. internal or external reference the max1270/max1271 operate with either an internal or external reference. an external reference is connect- ed to either ref or refadj (figure 13). the refadj internal buffer gain is trimmed to 1.638v to provide 4.096v at ref from a 2.5v reference.
max1270/max1271 internal reference the internally trimmed 2.50v reference is amplified through the refadj buffer to provide 4.096v at ref. bypass ref with a 4.7? capacitor to agnd and refadj with a 0.01? capacitor to agnd (figure 13a). the internal reference voltage is adjustable to ?.5% (?5 lsbs) with the reference-adjust circuit of figure 1. external reference to use the ref input directly, disable the internal buffer by tying refadj to v dd (figure 13b). using the refadj input eliminates the need to buffer the refer- ence externally. when a reference is applied at refadj, bypass refadj with a 0.01? capacitor to agnd. note that when an external reference is applied at refadj, the voltage at ref is given by: v ref = 1.6384 v refadj (2.4 < v ref < 4.18) (figure 13c). at ref and refadj, the input impedance is a minimum of 10k ? for dc currents. during conver- sions, an external reference at ref must be able to deliver 400? dc load currents and must have an out- put impedance of 10 ? or less. if the reference has higher output impedance or is noisy, bypass ref with a 4.7? capacitor to agnd as close to the chip as possi- ble. with an external reference voltage of less than 4.096v at ref or less than 2.5v at refadj, the increase in the ratio of rms noise to the lsb value (full-scale / 4096) results in performance degradation (loss of effective bits). multirange, +5v, 8-channel, serial 12-bit adcs 7-182 ___________________________________________________________________________________ cs sclk din dout a/d state ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 18 9 24 22 14 16 start sel2 sel1 sel0 bip rng pd1 pd0 d11 d10 d9 d7 d8 d6 d5 d4 d2 d3 d1 d0 start sel2 sel1 sel0 bip rng pd1 pd0 start sel0 sel1 sel2 control byte result control byte 1 control byte 2 13 sclk 13 sclk sstrb d10 d11 d9 d8 d6 d7 d5 d4 d3 result 1 acquisition conversion acquisition conversion high-z figure 11. internal clock mode, 13 clocks/conversion timing cs sclk din dout a/d state idle ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 18 9 24 25 32 16 17 start start sel2 sel1 sel0 bip rng pd1 pd0 d11 d10 d9 d7 d8 d6 d5 d4 d2 d3 d1 d0 start sel2 sel1 sel0 bip rng pd1 pd0 control byte result control byte 1 cb 2 16 sclk 16 sclk sstrb d10 d11 d9 d8 d6 d7 d5 d4 d3 result 1 acquisition conversion acquisition conversion high-z high-z high-z figure 12. internal clock mode, 16 clocks/conversion timing
power-down mode to save power, configure the converter into low-current shutdown mode between conversions. two program - mable power-down modes are available in addition to a hardware shutdown. select stbypd or fullpd by pro- gramming pd0 and pd1 in the input control byte (table 4). when software power-down is asserted, it becomes effective only after the end of conversion. for example, if the control byte contains pd1 = 0, then the chip will remain powered up. if pd1 = 1, then the chip will power-down at the end of conversion. in all power- down modes, the interface remains active and conver- sion results may be read. input overvoltage protection is active in all power-down modes. the first logical 1 on din after cs falls is interpreted as a start condition, and powers up the max1270/ max1271 from a software selected stbypd or fullpd condition. for hardware-controlled power-down (fullpd), pull shdn low. when hardware shutdown is asserted, it becomes effective immediately, and any conversion in progress is aborted. choosing power-down modes the bandgap reference and reference buffer remain active in stbypd mode, maintaining the voltage on the 4.7? capacitor at ref. this is a ?c?state that does not degrade after power-down of any duration. in fullpd mode, only the bandgap reference is active. connect a 33? capacitor between ref and agnd to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. throughput rates down to 1ksps can be achieved without allotting extra acquisition time for ref- erence recovery prior to conversion. this allows con- version to begin immediately after power-up. if the discharge of the ref capacitor during fullpd exceeds the desired limits for accuracy (less than a fraction of an lsb), run a stbypd power-down cycle prior to starting conversions. take into account that the reference buffer recharges the bypass capacitor at an 80mv/ms slew rate, and add 50? for settling time. auto-shutdown selecting stbypd on every conversion automatically shuts down the max1270/max1271 after each conver- sion without requiring any start-up time on the next con- version. max1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-183 ref 10k 2.5v 4.7 f c ref 0.01 f refadj a v = 1.638 max1270 max1271 figure 13a. internal reference ref v dd 10k 2.5v 4.096v 4.7 f c ref refadj a v = 1.638 max1270 max1271 figure 13b. external reference, reference at ref ref 10k 2.5v 4.7 f c ref 2.5v refadj a v = 1.638 0.01 f max1270 max1271 figure 13c. external reference, reference at refadj
max1270/max1271 transfer function output data coding for the max1270/max1271 is bina- ry in unipolar mode with 1lsb = (fs / 4096) and two? complement binary in bipolar mode with 1lsb = [(2 | fs | ) / 4096]. code transitions occur halfway between successive-integer lsb values. figures 14a and 14b show the input/output (i/o) transfer functions for unipo- lar and bipolar operations, respectively. for full-scale values, refer to table 3. layout, grounding, and bypassing careful printed circuit board layout is essential for best system performance. use a ground plane for best per- formance. to reduce crosstalk and noise injection, keep analog and digital signals separate. connect ana- log grounds and dgnd in a star configuration to agnd. for noise-free operation, ensure the ground return from agnd to the supply ground is low imped- ance and as short as possible. connect the logic grounds directly to the supply ground. bypass v dd with 0.1? and 4.7? capacitors to agnd to minimize high- and low-frequency fluctuations. if the supply is exces- sively noisy, connect a 5 ? resistor between the supply and v dd , as shown in figure 15. multirange, +5v, 8-channel, serial 12-bit adcs 7-184 ___________________________________________________________________________________ output code input voltage (lsb) 0 fs fs - 3 / 2 lsb 1 lsb = full-scale transition 123 11... 111 11... 110 11... 101 00... 011 00... 010 00... 001 00... 000 fs 4096 figure 14a. unipolar transfer function output code input voltage (lsb) 0 +fs - 1 lsb 1 lsb = -fs 011... 111 011... 110 000... 001 000... 000 111... 111 100... 010 100... 001 100... 000 2 ? fs ? 4096 figure 14b. bipolar transfer function v dd gnd dgnd dgnd agnd +5v +5v supply r* = 5 ? digital circuitry 4.7 f 0.1 f max1270 max1271 ** * optional ** connect agnd and dgnd with a ground plane or a short trace. figure 15. power-supply grounding connections
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-185 pin configurations 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 n.c. ref n.c. refadj dgnd n.c. dgnd v dd ch7 ch6 ch5 ch4 sstrb din cs sclk 16 15 14 13 9 10 11 12 ch3 ch2 ch1 ch0 agnd shdn dout n.c. dip max1270 max1271 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n.c. ref refadj n.c. n.c. ch7 ch0 n.c. ch6 ch5 ch4 ch3 ch2 ch1 agnd shdn dout n.c. sstrb din n.c. n.c. cs sclk n.c. dgnd dgnd v dd ssop top view max1270 max1271 ordering information (continued) chip information transistor count: 4219 substrate connected to agnd part max1270aeng max1270beng max1270aeai -40? to +85? -40? to +85? -40? to +85? temp. range pin-package 24 narrow plastic dip 24 narrow plastic dip 28 ssop inl (lsb) ?/2 ? ?/2 max1270beai -40? to +85? 28 ssop ? max1271 acng max1271bcng max1271acai 0? to +70? 0? to +70? 0? to +70? 24 narrow plastic dip 24 narrow plastic dip 28 ssop ?/2 ? ?/2 MAX1271BCAI 0? to +70? 28 ssop ? max1271aeng max1271beng max1271aeai -40? to +85? -40? to +85? -40? to +85? 24 narrow plastic dip 24 narrow plastic dip 28 ssop ?/2 ? ?/2 max1271beai -40? to +85? 28 ssop ?
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs 7-186 ___________________________________________________________________________________ ________________________________________________________package information pdipn.eps
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs ____________________________________________________________________________________ 7-187 package information (continued) ssop.eps
max1270/max1271 multirange, +5v , 8-channel, serial 12-bit adcs notes 7-188 ___________________________________________________________________________________

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